Non-volatile semiconductor memory devices that have an array of memory cells is a basic building block in computer systems and semiconductor devices that store data. Typical non-volatile memory arrays are arranged in rows and columns of memory cells (“cells”), where each cell in the array typically provides two different states, and each cell can be uniquely addressable. However, non-volatile memory cells that provide more than two possible states are also known.
Finding the threshold voltage (VT) or bit cell current (BCC) of the cells in the non-volatile memory of a semiconductor device is used in production testing for stability testing to ensure the long term reliability of the memory for holding data. For example, one example semiconductor device having non-volatile memory is a microcontroller (MCU) which generally includes a central processing unit (CPU) and a flash memory array as the main memory where the customer's firmware generally resides.
One type of known flash memory cell is based on a dual gate field effect transistor (FET) that includes a select gate, a floating gate, a body, a drain, and a source. For read operations, the source of the flash cell is coupled to ground, and the drain of the cell is coupled to a bitline of the flash memory array. The cell is switched on and off by applying a select voltage to the select gate via a wordline that is coupled to the select gate. The extent to which the cell conducts current when the select voltage is applied across the channel of the FET is determined by the threshold voltage VT of the cell, where the VT can be increased by trapping electrons on the floating gate.
A typical method for storing information in a flash cell involves trapping of excess electrons on the floating gate to increase the VT of the cell such that the channel current conducted by the cell is reduced when the select voltage is applied to the select gate. If the cell current is less than a reference current when the select voltage is applied, the cell is said to be “programmed.” If the cell current is greater than the reference current when the select voltage is applied, the flash cell is said to be “erased.” Since the typical flash memory cell is configured to be in one of two possible states, programmed or erased, the typical flash cell is said to store one bit of data.
The cells in the memory array are generally first set (initialized) to a predetermined bit pattern of ones (1; erased) and/or zeros (0; programmed) before each VT search and/or bit cell current (BCC) search. The memory arrays cells may be set to be all erased (FF) or at least partially programmed (00, checkerboard (CHK), or inverse CHK). Following setting of the states of the memory cells, during the VT/BCC search, an external control voltage/current is applied by automatic test equipment (ATE) to cells in the device and then the content of the all the cells in the array is read typically by the ATE and compared to the expected values from the predetermined bit pattern. In the case of memory testing an integrated circuit (IC) such as an MCU including a controller (e.g., central processing unit (CPU)) and a non-volatile memory array, the IC can include a dedicated analog test pin for receiving the voltage or current from the ATE for the read operation so that the MCU can perform the search and read functions. The MCU may also generate the voltage or current levels for the read operation and perform the search and read functions, thus removing the need for the ATE for testing the memory array. A PASS is observed when all of the memory cells match with the expected value at one end of the search range, or the test is considered a FAIL otherwise at another end of the search range.
Based on the compare results, in the case of a FAIL, the external conditions (e.g., control voltage for VT testing) may be adjusted up or down by a predetermined fixed step size (e.g., 10 mV for VT testing) until the actual value read for all the cells in the array match with the expected value at the target resolution level for the search (thus providing a “convergence value”). Using a binary search scheme for conventional cells providing 2 states, this process typically involves multiple, iterative passes of reading all the cells in the memory array several times (stages) to find the convergence value, driving the test cost higher than desired.